The present invention relates generally to semiconductor devices and particularly to improving lateral double diffused metal oxide semiconductor (LDMOS) devices.
LDMOS are well known devices, which form an integral part of modern day display panels, telecommunication systems, motor controllers, switch lock power supplies, inverters, and alike, designed for low on-resistance and high blocking voltage. The high voltage (HV) characteristics associated with these applications require that the LDMOS devices have the capacity to withstand voltages, which may vary from about 5V to about 1000V without exhibiting breakdown.
LDMOS devices are field effect transistor (FET) devices which bear a certain resemblance to conventional FET devices insofar as they also include a pair of source/drain regions formed within a semiconductor substrate and separated in part by a channel region also formed within the semiconductor substrate, the channel region in turn having formed thereover a gate electrode. However, LDMOS devices differ from conventional FET devices in part insofar as while a pair of source/drain regions within a FET device is typically fabricated symmetrically with respect to a gate electrode within the FET device, within a LDMOS device a drain region is formed further separated from a gate electrode than a source region, and the drain region is additionally formed within a doped well (of equivalent polarity with the drain region) which separates the drain region from the channel region.
An LDMOS device is basically an asymmetric power MOSFET fabricated using a double diffusion process with coplanar drain and source regions. The low on-resistance and high blocking voltage features of the LDMOS are obtained by creating a diffused P-type channel region in a low-doped N-type drain region. The source and drain regions are on the laterally opposing sides of the gate area. The concentrations of doping are denoted by N− and N+ for n-doped material (n-material), and by P+ and P− for p-doped material (p-material). The low doping on the drain side results in a large depletion layer with high blocking voltage. The channel region diffusion can be defined with the same mask as the source region, resulting in a short channel with high current handling capability. The device may be fabricated by diffusion as well as ion implantation techniques.
A typical structure of an LDMOS device 100, according to the prior art is shown in FIG. 1. N-well of silicon 112 is isolated from P-well 111 by boundaries 113. P-well 111 extends downwards from the top surface and includes N+regions 117 whose distance L 110 from the junction between P-well 111 and N-well 112 defines the channel. The N+regions 117 provide both source 125 and drain 130 contact regions. With the application of positive voltage VG polysilicon gate 116 (beneath which is a layer of gate oxide not explicitly shown), current can flow through the channel from the source 125 into N+ 117, into P-well 111, and into N-well 112 to be collected at N+ 117 by the drain 130. Metal contact 115 shorts N+ 117 to P+ohmic contact 119. This allows source current to be applied through the P-well 111 which can then be cooled through a heat sink. Most LDMOS structures are built on a substrate having one or more other device structures. These devices are isolated by utilizing field oxide (FOX) processes or shallow trench isolation (STI) regions. The role of FOX regions 114 in HV applications is to provide isolation and improve breakdown voltage by reducing electric field density.
Presently, many HV LDMOS devices include a wide drift region (N/P well) having a length D 120 that is required to isolate cool drain (high voltage) and hot well (GND). The typical value of D 120, which is measured from an edge of the drain 130 to the boundary 113 of the N/P well, is set as 5 microns (μm) to prevent high voltage drain 130 punch through to the base guard ring 135 (GND). However, due to the large dimension D 120 of the drift region, e.g., 5 μm, the LDMOS may be inadvertently disabled due to parasitic bipolar action. In addition, the large dimension D 120 of the drift region also increases the size of the LDMOS device.
Thus, a need exists to provide an improved LDMOS device that offers: a) an improved technique to constrain the electric field in the drift region between the cool drain (hot voltage) and hot well (GND), and b) a reduced dimension of the drift region thereby reducing the device size.